RESEARCH / 77 K

From neural-rendering accelerators to cryogenic GPU systems.

My current work studies how device- and system-level changes at 77 K reshape GPU resource allocation and AI workloads. Earlier neural-rendering work remains the methodological origin, not the current destination.

Current question

Where should the cryogenic dividend go?

The ongoing work follows an evidence-first chain: normalize cryogenic measurements, synthesize bounded parameters, characterize representative workloads, and explore architecture choices in reproducible simulation. No unpublished results are disclosed here.

EVIDENCE
77 K / 300 K
PARAMETERS
Bounded synthesis
WORKLOADS
Trace & characterize
ARCHITECTURE
Explore & explain

Trajectory

01

2026 — NOW

Cryogenic GPU Systems

Building a reproducible chain from evidence and parameter synthesis to GPU tracing, simulation, and design-space exploration at 77 K.
02

2024 — 2026

GPU architecture and systems

Expanding from individual neural-rendering accelerators toward workloads, memory hierarchies, scheduling, and system modeling.
03

2022 — 2025

Neural-rendering acceleration

Research spanning algorithm analysis and hardware design for ray representation, sampling, data reuse, and conflict-free encoding.

PUBLICATIONS

Selected publications

Existing publications document the earlier neural-rendering and accelerator phase.

Full publication archive
2026

An Energy-Efficient Edge Coprocessor for Neural Rendering With Explicit Data Reuse Strategies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

B. Yuan, X. Zhang, Z. Zheng, Y. Zhang, H. Wan, Z. Yuan, J. Chen, Yunxiang He, J. Ding, X. Zhang, C. Rao, W. Su, P. Zhou, J. Yu, X. Lou

2026

SCAR: A Neural Rendering Accelerator with Sparse-Aware Sampling and Conflict-Free Encoding

ISCAS

Yunxiang He, Yongzhi Zhang, Quanyu Chen, Chaofan Li, Qihan Ding, Xin Lou

2025

A Neural Rendering Coprocessor With Optimized Ray Representation and Marching

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Z. Yuan, B. Yuan, C. Rao, Y. Zhu, Yunxiang He, P. Zhou, J. Yu, X. Lou

2024

Density Estimation-based Effective Sampling Strategy for Neural Rendering

IEEE International Symposium on Circuits and Systems (ISCAS)

Yunxiang He, X. Lou

2024

A 0.59μJ/pixel High-throughput Energy-efficient Neural Volume Rendering Accelerator on FPGA

IEEE Custom Integrated Circuits Conference (CICC)

Z. Yuan, B. Yuan, Y. Gu, Y. Zheng, Yunxiang He, X. Wang, C. Rao, P. Zhou, J. Yu, X. Lou

2024

An Efficient Hardware Volume Renderer for Convolutional Neural Radiance Fields

IEEE International Symposium on Circuits and Systems (ISCAS)

X. Wang, Yunxiang He, X. Zhang, P. Zhou, X. Lou

2024

Ray Reordering for Hardware-Accelerated Neural Volume Rendering

IEEE Transactions on Circuits and Systems for Video Technology (TCSVT)

J. Ding, Yunxiang He, B. Yuan, Z. Yuan, P. Zhou, J. Yu, X. Lou

2023

Analysis and Design of Precision-scalable Computation Array for Efficient Neural Radiance Field Rendering

IEEE Transactions on Circuits and Systems I: Regular Papers

K. Long, C. Rao, Yunxiang He, Z. Yuan, P. Zhou, J. Yu, X. Lou